1. Field
The disclosed embodiments relate to a method of optimizing data training and, more particularly, to a method of optimizing data training in a system including memory devices.
2. Description of Related Art
Rapid increases in the capacity and operating speed of memory devices have led to increases in skews due to differences in transmission rate between data and clock signals. Here, the term “skew” refers to a phase difference between a clock signal and the data.
In general, a memory device may employ a data training method as a clock data recovery (CDR) method to remove a skew between data and a clock signal. Data training methods may be classified into a per-pin data training method and a byte data training method. The per-pin data training method may include compensating a skew between a clock signal and each of a plurality of data transmitted in parallel. The byte data training method may include selecting one from a plurality of data transmitted in parallel, compensating a skew between a clock signal and the selected data, and applying a compensation result to all the remaining data.
Either of the per-pin data training method and the byte data training method may be categorized as a write data training method or a read data training method. In the write data training method, a memory controller may generate training data having a data training pattern and transmit the training data to a memory device to perform data training. The pattern may be compared to a predetermined pattern to determine if errors exist and to determine a data skew. An exemplary data training method is described in U.S. Patent Application Publication No. 2006/0062286, published on Mar. 23, 2006, and incorporated herein by reference in its entirety. In the read data training method, training data stored in a training register of a memory device may be transmitted to a memory controller to perform data training. However, the read training method may be performed using training data stored in a training register, while the write training method may be performed using training data generated by a memory controller. As a result, both the read data training operation and the write data training operation may be performed irrespective of enabling states of a plurality of banks included in the memory device. Thus, a conventional data training method may be performed when the plurality of banks included in the memory device are disabled.
Accordingly, in the conventional data training method, data training may be performed without consideration of a core noise caused in the memory device, and a skew between a clock signal and data may be controlled based on the data training result. However, as the operating speed of the memory device further increases, the influence of the core noise of the memory device cannot be ignored.